PHYSICAL DESIGN

Inputs and Outputs at each stage of PD Flow.

Floorplanning:

Inputs:

·         Design Setup

·         Gate Level Netlist

·         Milky way reference Library

·         SDC (Synopsis Design Constraints)

·         TDF (Top Design File)

Outputs:

·         Floorplanned Cell

Checks:

·         Is Macro orientation correct

·         Is placement Legality (i.e. Cell overlaps, cells outside the core boundary ) fine

·         Is Macro placement is according to macro placement guidelines?

·         Placing Macros using Data Flow diagram and by fly-line analysis.

Goal:

·         Goal is to provide continuous area for Standard Cells to be place.

·         The Macro placement should not lead to Congestion.

Power Planning:

 Inputs:

·         Floor planned Cell

·         Power Budget

·         The top level Engineer may freeze the step , stop, width of Vertical Straps (Because we are designing a block which is going to fit in some chip so the Vertical straps in the chip nd in our block should match, dats the reason In Block level design the top engineer gives us the Vertical straps constraints) {M6pwr.tcl}

Outputs:

·         Power Mesh is Synthesized with IR Drop less than 5 % {VDD+VSS}

·         Floor Planned Cell with Power Mesh

            Checks:

·         Check Whether u have met the Required IR Drop

·         Verify PG connections to check for floating shapes or floating pins  {We also call this as checking for Power DRC’s, it’s good to use this term}

·         Check whether the Placement Legality is fine.

 Goal:

·         To meet the Required IR Drop (WHY ??? Bcoz the Acceptable Voltage should reach all the cells in the design to work properly. If the IR drop is more to a certain region then the there is no sufficient DC voltage for the cell in that region to Bias properly)

Placement:

 Inputs:

·         Floor planned Cell

·         Constraints like don’t touch cells (might be already written in SDC ) if not u need to give the cells which u don’t want them to be removed during placement optimization.

·         Skew file {in second iteration we have generated a skew file and then we have sourced it again to meet Timing violations by adding USEFUL SKEW}

 Pre requisites for Placement:

·         First of all there should be continuous area for standard cells and the power n/w should be synthesized with the acceptable IR drop.

·         Decide whether u gonna do timing driven placement or congestion driven placement or area driven placement or combo ..

Checks:

·         Check the timing Reports nd analyze them

·         Check the Placement Legality

·         Check for Global Route Congestion ( if there are too many Hot spots (Red color regions) then there is problem with floor plan , we need to do beginning from the floor plan.

·         Is Std cell Placement Utilization Ok..???

Goal:

·         Trying to meet as many setup violations as possible.

·         Should have acceptable std cell placement utilization

·         Should be Congestion Free.

Clock Tree Synthesis:

Inputs:

·         Placed Cell

·         CTS Constraints

·         Non Default Routing Rules {NDR , Bcoz during clock signal (routingclock_route.tcl) Clock nets are largely proned to Cross Talk effect, so apart from the default rounting rules in the Technology Library, we need to take Double spacing , nd clock shielding for clock nets, these rules are der in NDR’s}

Goal:

·         To Balance Insertion Delay

·         To make Skew Zero.

For this we this reason we will need to synthesize the clock tree

·         After CTS you should meet all the Hold Violations

Checks:

·         IS Skew is minimum and Insertion delay balanced.

·         IS Timing {Especially Hold} met, if not why…???

·         If there are timing violations are all the constraints constrained properly.{like not defining false paths, asynchronous paths, multicycle paths}.

·         IS std Cell Utilization acceptable at this stage

·         Check for Global Route Congestion

·         Check for Placement Legality.

Q] Inputs to floor plan:
   1) Mapped Design (netlist)
   2) logical libraries and physical libraries
   3) SDC(timing constranits)

Q]Libraries needed in Physical Design
  *.lib library
  *Technology library
  *Milky way reference library
  *Technology look up file(TLUPLUS)
  *Top Design File

Q]What are logical libraries?
   IC compiler extracts the timing information and the functional information
   of the standard cells from the .lib library (logical libraries)

   Logical libraries also contain the timing infortion about the macros(ex RAM)

Q]What is Technlogy library?
   Technolgy library contains the informtion about the layouts of standard cells
   Ex:- .tf  library

Q]What are the Physical libraries?
   As logical libraries contain info about the timing information and
   functional information about the standard cells , Physical libraries
   contain the Physical information about the standard cells

Q]What is the Physical information about the Standard cells?
    Layout information about Standard cells (contained in Technnology library (.tf))
   TLUPlus is a binary table format that sores the RC coefficients. The
   TLUPlus models enable accurate RC extraction results by including the
   effect of width, space, density and temperature on the resistance coefficients.

Q]What is Back Annotation?

  This term is in general used in connection to netlist simulations and STA where the propagation delay(s)
  through each cell in the netlist is overridden by the delay value(s) specified in a special file
  called sdf(synopsys delay format) file. The process of putting delays from a given source for the
  cells in a netlist during netlist simulation is called Back Annotation. Normally the values of the
  delays corresponding to each cell in the netlist would come from the simulation library i.e verilog
  model of library cells. But those delays are not the actual delays of cells, as each of them is instantiated
  in a netlist in different surroundings, different physical locations, different loads, different fan in.
  The delay of two similar cells in the netlist at two different physical locations in a chip can be significantly
  different depending upon above said factors. Therefore in order to have actual delays for the cells
  in your netlist, an SDF is written out, by a EDA tool can be a synthesis tool or a layout tool etc..
  which contains the delays of each instance of each library cell  in the netlist, under the circumstances the cell      is in.
  During simulations or Static Timing Analysis, each cell in the netlist gets its correponding delay read, or      more
  technically 'annotated' from the SDF file.

  SDF file contains the delay value of each timing arc
  corresponding to each cell in the netlist. These delay values in the SDF file are extracted
  under a given conditions of the netlist. It may be that the SDF corresponds to just an after
  synthesis netlist, with wire loads estimated according to some wire load model, or it may
  be that the SDF corresponds to a neltist which has been laid out, with actual position of cell,
  actual load on the cell, actual metal wires connected to the cells.